BYTE, WORD, and LONG INSTRUCTIONS

TWO and THREE OPERAND GROUP
Descriptions (x equals B, W, or L)

ADDx2

add,sum

sum

sum + add

ADD

ADDx3

add1,add2,sum

sum

add1 + add2

ADD

SUBx2

sub,dif

dif

dif - sub

SUBtract

SUBx3

sub,min,dif

dif

min - sub

SUBtract

MULx2

mulr,prd

prd

prd * mulr

MULtipiу

MULx3

mulr,muld,prd

prd

muld * mulr

MULtiply

DIVx2

divd,quo

quo

quo / divd

DIVide

DIVx3

divr,divd,quo

quo

divd / divr

DIVide

BICx2

mask,dst

dst

~dst AND mask

BIt Clear

BICx3

mask,src,dst

dst

~src AND mask

BIt Clear

BISx2

mask,dst

dst

dst OR mask

BIt Set (OR)

BISx3

mask,src,dst

dst

src OR mask

BIt Set (OR)

XORx2

mask,dst

dst

dst EXOR mask

eXclusive OR

XORx3

mask,src,dst

dst

src EXOR mask

eXclusive OR

Operation Codes

 

Byte-2

Byte-3

Word-2

Word-3

Long-2

Long-3

N

Z

V

C

ADD

ADDB2

ADDB3

ADDW2

ADDW3

ADDL2

ADDL3

*

*

*

*

SUB

SUBB2

SUBB3

SUBW2

SUBW3

SUBL2

SUBL3

*

*

*

*

MUL

MULB2

MULB3

MULW2

MULW3

MULL2

MULL3

*

*

*

0

DIV

DIVB2

DIVB3

DIVW2

DIVW3

DIVL2

DIVL3

*

*

*

0

BIC

BICB2

BICB3

BICW2

BICW3

BICL2

BICL3

*

*

0

-

BIS

ВISB2

BISB3

BISW2

BISW3

BISL2

BISL3

*

*

0

-

XOR

XORB2

XORB3

XORW2

XORW3

XORL2

XORL3

*

*

0

-

TWO OPERAND GROUP
Descriptions (x equals B, W, or L)

MOVx

src,dst

dst

src

MOVe

MNEGx

src,dst

dst

-src

Move NEGative

MCOMx

src,dst

dst

~src

Move COMplement

MOVAx

src,dst

dst

ADR(src)

MOVe Address

BITx

mask,src

tmp

~src AND mask

BIt Test (AND)

CMPx

src1,src2

tmp

src1 - src2

CoMPare

MOVZBx

src,dst

dst

ZEROS ! src

Zero extend Byte

MOVZWx

src,dst

dst

ZEROS ! src

Zero extend Word

Operation Codes

 

Byte

Word

Long

N

Z

V

C

 

MOVx

MOVB

MOVW

MOVL

*

*

0

-

 

MNEGx

MNEGB

MNEGW

MNEGL

*

*

*

*

* reflects result

MCOMx

MCOMB

MCOMW

MCOML

*

*

0

-

 

MOVAx

MOVAB

MOVAW

MOVAL

*

*

0

-

- unchanged

BITx

BITB

BITW

BITL

*

*

0

-

 

CMPx

CMPB

CMPW

CMPL

*

*

0

-

0 cleared to zero

MOVZBx

 

MOVZBW

MOVZBL

0

*

0

-

 

MOVZWx

 

 

MOVZWL

0

*

0

-

1 set to one

SINGLE OPERAND GROUP
Descriptions (x equals B, W, or L)

INCx

dst

dst

dst + 1

INCrement

DECx

dst

dst

dst - 1

DECrement

CLRx

dst

dst

0

CLeaR

TSTx

src

tmp

src

TeST (set N, Z, V, C)

PUSHAx

src

MOVAx src,-(SP)

PUSH Address on stack

Operation Codes

 

Byte

Word

Long

N

Z

V

C

INCx

INCB

INCW

INCL

*

*

*

*

DECx

DECB

DECW

DECL

*

*

*

*

CLRx

CLRB

CLRW

CLRL

0

1

0

-

TSTx

TSTB

TSTW

TSTL

*

*

0

0

PUSHAx

PUSHAB

PUSHAW

PUSHAL

*

*

0

-

ADD, COMPARE, and BRANCH INSTRUCTIONS (N=Z=V=*, C=-)

ACBB

 

index ← index + add, branch

ACBW

limit,add,index,disp

if add GEQ 0 and index LEQ limit

ACBL

 

or add LSS 0 and index GEQ limit


FLOATING POINT INSTRUCTIONS

FLOATING POINT FORMATS

 

F_flt

D_flt

G_flt

H_flt

exponent bits

8

8

11

15

fraction bits

23

55

52

112

total bits

32

64

64

128

TWO and THREE OPERAND GROUP
Descriptions (x equals F, D, G, or H)

ADDx2

add,sum

sum

sum + add

ADD

АDDх3

add1,add2,sum

sum

add1 + add2

ADD

SUBx2

sub,dif

dif

dif - sub

SUBtract

SUBx3

sub,min,dif

dif

min - sub

SUBtract

MULx2

mulr,prd

prd

prd * mulr

MULtiply

MULx3

mulr,muld,prd

prd

muld * mulr

MULtiply

DIVx2

divd,quo

quo

quo / divd

DIVide

DIVx3

divr,divd,quo

quo

divd / divr

DIVide

Operation Codes

 

F_flt

D_flt

G_flt

H_flt

N

Z

V

C

ADDx2

ADDF2

ADDD2

ADDG2

ADDH2

*

*

*

0

ADDx3

ADDF3

ADDD3

ADDG3

ADDH3

*

*

*

0

SUBx2

SUBF2

SUBD2

SUBG2

SUBH2

*

*

*

0

SUBx3

SUBF3

SUBD3

SUBG3

SUBH3

*

*

*

0

MULx2

MULF2

MULD2

MULG2

MULH2

*

*

*

0

MULx3

MULF3

MULD3

MULG3

MULH3

*

*

*

0

DIVx2

DIVF2

DIVD2

DIVG2

DIVH2

*

*

*

0

DIVx3

DIVF3

DIVD3

DIVG3

DIVH3

*

*

*

0

TWO OPERAND INSTRUCTIONS
Descriptions (x equals F, D, G, or H)

MOVx

src,dst

dst

src

MOVe

MOVAx

src,dst

dst

adr(src)

MOVe Address

MNEGx

src,dst

dst

-src

Move NEGative

CMPx

src1,src2

tmp

src2 - src1

CoMPare

Operation Codes

 

F_flt

D_flt

G_flt

H_flt

N

Z

V

C

MOVx

MOVF

MOVD

MOVG

MOVH

*

*

0

-

MOVAx

MOVAF

MOVAD

MOVAG

MOVAH

*

*

0

-

MNEGx

MNEGF

MNEGD

MNEGG

MNEGH

*

*

0

0

CMPx

CMPF

CMPD

CMPG

CMPH

*

*

0

0

SINGLE OPERAND INSTRUCTIONS (x equals F, D, G, or H)
Descriptions

CLRx

dst

dst

0

CLeaR

TSTx

src

tmp

src

TeST (set N, Z, V, C)

PUSHAx

src

MOVAx src,-(SP)

PUSH Address on stack

Operation Codes

 

F_flt

D_flt

G_flt

H_flt

N

Z

V

C

CLRx

CLRF

CLRD

CLRG

CLRH

0

1

0

-

TSTx

TSTF

TSTD

TSTG

TSTH

*

*

0

0

PUSHAx

PUSHAF

PUSHAD

PUSHAG

PUSHAH

*

*

0

-

ADD, COMPARE, and BRANCH INSTRUCTIONS (N=Z=V=*, C is unchanged)

ACBF

 

index ← index + add, branch

ACBD

limit,add,index,disp

if add GEQ 0 and index LEQ limit

ACBG

 

or add LSS 0 and index GEQ limit

ACBH

 

 

OTHER INSTRUCTIONS (x equals F, D, G, or H)

EMODx

mulr,add,index,disp

Extend MODulus (multiply)
(see Chapter 12.6)

POLYx

arg,degree,tbladr

evaluate POLYnomial
(see Chapter 12.6)


BRANCH, JUMP, CALL, and CASE INSTRUCTIONS

(Unless noted otherwise, operand is one byte displacement)

SIGNED and UNSIGNED BRANCH INSTRUCTIONS

Signed Branch
Instructions

Unsigned Branch
Instructions

 

BEQL

BEQLU

Branch if EQual

BNEQ

BNEQU

Branch if Not EQual

BLSS

BLSSU

Branch if LeSS

BGTR

BGTRU

Branch if GreaTeR

BLEQ

BLEQU

Branch if Less or EQual

BGEQ

BGEQU

Branch if Greater or EQual

CONDITION CODE BRANCH INSTRUCTIONS

BNEQ

Branch if Z Clear (result Not EQual to zero)

BEQL

Branch if Z Set (result EQuaL to zero)

BCC

Branch if C Clear (no unsigned overflow)

BCS

Branch if C Set (signed overflow)

BVC

Branch if V Clear (no signed overflow)

BVS

Branch if V Set (signed overflow)

BGEQ

Branch if N Clear (result is not negative)

BLSS

Branch if N Set (result is negative)

UNCONDITIONAL BRANCHES and JUMPS

BRB

disp

BRanch with Byte displacement

BRW

disp

BRanch with Word displacement

JMP

adr

JuMP (general operand specifier)

SUBROUTINE CALLS and RETURN

BSBB

disp

Branch to SuBroutine with Byte displacement

BSBW

disp

Branch to SuBroutine with Word displacement

JSB

adr

Jump to SuBroutine (general operand specifier)

RSB

 

Return from SuBroutine (no operand)

PROCEDURE CALLS and RETURN (See Chapter 9)

CALLG

arglist,dst

CALL procedure with General arg list

CALLS

numarg,dst

CALL procedure with arguments on Stack

RET

 

RETurn from procedure

ADD, COMPARE, and BRANCH INSTRUCTIONS
(N=Z=V=*, C=-)
(disp is a word displacement)

 

 

index ← index + add, branch

АСВx

limit,add,index,disp

if add GEQ 0 and index LEQ limit

 

 

or add LSS 0 and index GEQ limit

 

 

Byte

Word

Long

F_flt

D_flt

G_flt

H_flt

 

ACBB

ACBW

ACBL

ACBF

ACBD

ACBG

ACBH

ADD or SUBTRACT ONE and BRANCH INSTRUCTIONS
(disp is a byte displacement, lim and index are longwords)

AOBLSS

lim,index,disp

index = index + 1, BR if index LSS lim

AOBLEQ

lim,index,disp

index = index + 1, BR if index LEQ lim

SOBGTR

index,disp

index = index - 1, BR if index GTR 0

SOBGEQ

index,disp

index = index – 1, BR if index GEQ 0

BRANCH ON LOW BIT (src Is a longword)

BLBC

src,disp

branch if low bit (bit 0) clear

BLBS

src,disp

branch if low bit (bit 0) set

CASE INSTRUCTIONS (for multiway branching)

CASEB

str,index,lim,disp[0],

tmp ← index - str

CASEW

              disp[1],

if tmp LEQU lim, BR disp[tmp]

CASEL

              disp[lim]

else no branch

BIT STRING BRANCH INSTRUCTIONS - see Bit String Instructions


LONGWORD (but not byte or word) INSTRUCTIONS

ADWC

add,sum

sum

sum + add + C

ADd With Carry

SBWC

sub,dif

dif

dif - sub - C

SuBtract With Carry

ASHL

cnt,src,dst

dst

src * 2**cnt

Arithmetic SHift Long

ROTL

cnt,src,dst

dst

ROTATE(src)

ROTate Long cnt bits

PUSHL

src

-(SP)

src

PUSH Long

INDEX

sub,low,high,size,indexin,indexout

see COMPUTE INDEX


QUADWORD AND OCTAWORD INSTRUCTIONS

ASHQ

cnt,src,dst

dst

src * 2**cnt

Arithmetic SHift

CLRQ

dst

dst

0

CLeaR

CLRO

dst

dst

0

CLeaR

MOVQ

src,dst

dst

src

MOVe

MOVO

src,dst

dst

src

MOVe

MOVAQ

src,dst

dst

ADR(src)

MOVe Address

MOVAO

src,dst

dst

ADR(src)

MOVe Address

PUSHAQ

src

-(SP)

ADR(src)

PUSH Address

PUSHAO

src

-(SP)

ADR(src)

PUSH Address

EMUL

mulr,muld,add,prod

Extended MULtiply (see Ch 6.3)

EDIV

divr,divd,quo,rem

Extended DIVide (see Ch 6.3)


COMPUTE INDEX

INDEX

sub,low,high,size,indexin,indexout (see Chapter 7.6)

 

indexout ← (indexin + sub*size)

 

if indexout LSS low or indexout GTR high, trap


SIGNED CONVERT INSTRUCTIONS excluding Packed (N=Z=V=*,C=0)

Description

CVTxy

src,dst

dst

src

ConVerT src (type x)

Instructions

to

Byte

Word

Long

F_flt

D_flt

G_flt

H_flt

from

 

 

 

 

 

 

 

Byte

 

CVTBW

CVTBL

CVTBF

CVTBD

CVTBG

CVTBH

Word

CVTWB

 

CVTWL

CVTWF

CVTWD

CVTWG

CVTWH

Long

CVTLB

CVTLW

 

CVTLF

CVTLD

CVTLG

CVTLH

F_flt

CVTFB

CVTFW

CVTFL

 

CVTFD

CVTFG

CVTFH

D_flt

CVTDB

CVTDW

CVTDL

CVTDF

 

 

CVTDH

G_flt

CVTGB

CVTGW

CVTGL

CVTGF

 

 

CVTGH

H_flt

CVTHB

CVTHW

CVTHL

CVTHF

CVTHD

CVTHG

 


PACKED CONVERT INSTRUCTIONS (N=Z=V=*,C=0)

to

Packed

Long

Leading

Trailing

from

 

 

 

 

Packed

 

CVTPL

CVTPS

CVTPT

Long

CVTLP

 

 

 

Leading

CVTSP

 

 

 

Trailing

CVTTP

 

 

 


OTHER CONVERSIONS

UNSIGNED CONVERSIONS
(MOve Zero extended)

to

Word

Long

from

 

 

Byte

MOVZBW

MOVZBL

Word

 

MOVZWL

FLOATING to LONGWORD
ROUNDED CONVERSIONS

to

Long

from

 

F_flt

CVTRFL

D_flt

CVTRDL

G_flt

CVTRGL

H_flt

CVTRHL



CHARACTER STRING INSTRUCTIONS (See Section 13.2)

A character string (str) is specified by a starting address (adr) and a 16-bit word that specifies the length in bytes (len)

CMPC3

len,adr1,adr2
R0  R1   R3

CoMPare Characters

CMPC5

len1,adr1,fill,len2,adr2
R0   R1        R2   R3

CoMPare Characters, (pad shorter with fill)

MOVC3

len,adr1,adr2
R0  R1   R3

MOVe Characters

MOVC5

len1,adr1,fill,len2,adr2
R0   R1        R2   R3

MOVe Characters, pad str1 if necessary

MOVTC

len1,adr1,table,len2,adr2
R0   R1   R3    R4   R5

MOVe Translated Characters (using 256 byte table)

MOVTUC

len1,adr1,byte,table,len2,adr2
R0   R1        R3    R4   R5

MOVe Trans. Until Char. stop if table(chr) EQ byte

LOCC

byte,len,adr
     R0  R1

LOCate first Character in str equal to byte

SKPC

byte,len,adr
     R0  R1

SKiP Characters in str equal to byte

SCANC

len,adr,table,mask
R0  R1  R3

SCAN Char, (find chr where mask AND table(chr) NE 0)

SPANC

len,adr,table,mask
R0  R1  R3

SPAN Char, (find chr where mask AND table(chr) EQ 0)

MATCHC

len1,adr1,len2,adr2
R0   R1   R2   R3

MATCH Characters (find first occurance of str2 in str1)


RACKED DECIMAL INSTRUCTIONS (See Section 13.3)

A decimal string (str) is specified by a starting address (adr) and a length (len) which is the number of decimal digits in the string. Packed decimal instructions use R0 through R3 or R0 through R5.

ARITHMETIC INSTRUCTIONS

MOVP

len,adr1,adr2

str2 ← str1

MOVe

CMPP3

len,adr1,adr2

tmp ← str1 - str2

CoMPare

CMPP4

len1,adr1,len2,adr2

tmp ← str1 - str2

CoMPare

ADDP4

len1,adr1,len2,adr2

str2 ← str2 + str1

ADD

SUBP4

len1,adr1,len2,adr2

str2 ← str2 - str1

SUBtract

ADDP6

len1,adr1,len2,adr2,len3,adr3

str3 ← str2 * str1

SUBP6

len1,adr1,len2,adr2,len3,adr3

str3 ← str2 - str1

MULP

len1,adr1,len2,adr2,len3,adr3

str3 ← str2 * str1

DIVP

len1,adr1,len2,adr2,len3,adr3

str3 ← str2 / str1

ASHP

cnt,len1,adr1,rnd,len2,adr2

str2 ← str1 * 10**cnt

PACKED CONVERT INSTRUCTIONS
(to and from Longwords, leading Separate numeric strings, and Trailing numeric strings)

CVTPL

len1,adr1,long

long ← str1

CVT Packed to Long

CVTLP

long,len1,adr1

str1 ← long

CVT Long to Packed

CVTPT

len1,adr1,tbl,len2,adr2

str2 ← str1

CVT Packed to T or
  S numeric string

CVTPS

len1,adr1,1en2,adr2

str2 ← str1

CVTTP

len1,adr1,tbl,len2,adr2

str2 ← str1

CVT T or S numeric
  string to Packed

CVTSP

len1,adr1,len2,adr2

str2 ← str1


QUEUE INSTRUCTIONS (see Section 13.9)

ABSOLUTE QUEUES (pointer is 32 bit absolute address)

INSQUE

entry,head

INSert at head of absolute QUEue

INSQUE

entry,@head+4

INSert at tail of absolute QUEue

REMQUE

entry,head

REMove at head of absolute QUEue

REMQUE

entry,@head+4

REMove at tail of absolute QUEue

RELATIVE QUEUES (pointer is 32 bit displacement)

INSQHI

entry,head

INSert into rel. Queue at Head Interlocked

INSQTI

entry,head

INSert into rel. Queue at Tail Interlocked

REMQHI

entry,head

REMove from rel. Queue at Head Interlocked

REMQTI

entry,head

REMove from rel. Queue at Tail Interlocked


EDIT INSTRUCTIONS (see Section 13.4)

EDIT

len1,adr1,pattern,adr2

str2 ← EDITED(str1)

 

 

str1 is packed decimal
str2 is a character string

EDIT PATTERN OPERATORS

Load fill and sign buffers

EO$LOAD_FILL

char

load the fill register (usually #^A" ")

EO$LOAD_SIGN

char

unconditionally load sign register

EO$LOAD_PLUS

char

load sign if str1 GTR 0 (#^A" " or #^A"+")

EO$LOAD_MINUS

char

load sign if str1 LSS 0 (#^A"-")

Output regardless of significance

EO$STORE_SIGN

 

output the sign character

EO$FILL

cnt

output cnt fill characters (cnt < 16)

Change significance (significance set by non-zero digit in str1)

EO$SET_SIGNIF

set significance

EO$CLEAR_SIGNIF

clear significance

Output digit or character (or fill if significance clear)

EO$INSERT

char

insert character (or fill)

EO$MOVE

cnt

copy digits from str1 to str2 (cnt < 16)

Float sign over insignificant digits (until significance set)

EO$FLOAT

cnt

EO$INSERT, but output sign on significance

EO$END_FLOAT

 

EO$STORE_SIGN if significance not yet set

Miscellaneous (see VAX Architecture Handbook)

EO$BLANK_ZERO

cnt

Store fill in prev. cnt bytes if str1 EQ 0

EO$REPLACE_SIGN

cnt

Store fill in byte (.-cnt) if str1 EQ 0.

EO$ADJUST_INPUT

cnt

Fudge str1 to length cnt (add or del zeros)

EO$END

 

MUST terminate string of pattern operators


BIT FIELD INSTRUCTIONS

OPERANDS

б и т о в о е   п о л е длина в битах (len) базовый адрес (adr) смещение в битах (ofs)

The offset (off) is a longword and the length (len) is a byte. Z in the operation code implies Zero extend (unsigned field).

INSTRUCTIONS.

FFC

off,len,adr,long

Find First Clear bit (long gets offset)

FFS

off,len,adr,long

Find First Set bit (long gets offset)

EXTV

off,len,adr long

long ← field

EXTract field

EXTZV

off,len,adr,long

long ← field

EXTract field

INSV

long,off,len,adr

field ← long

INSert field

CMPV

off,len,adr,long

tmp ← field - long

CoMPare field

CMPZV

off,len,adr,long

tmp ← field - long

CoMPare field


STACK OPERATIONS

POPR

word

POP Registers (word is a 16-bit register mask)

PUSHR

word

PUSH Registers (word is a 16 bit register mask)

PUSHL

long

PUSH Longword

PUSHAx

oper

PUSH Address of oper (x = Byte, Word, Long, Quad, Octa, F_flt, D_flt, G_flt, or H_flt)


PROCESSOR STATUS INSTRUCTIONS

PROCESSOR STATUS LONGWORD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 <---- Не используется ----> Системные функции, см. главу 14 <----------------- слово состояния процессора ----------------> a b c d N Z V C

a. decimal overflow trap bit
b. floating underflow trap bit
c. integer overflow trap bit
d. trace trap bit

INSTRUCTIONS

BICPSW

mask

BIC mask,PSW

Bit Clear, Processor Status Word

BISPSW

mask

BIS mask,PSW

Bit Set, Processor Status Word

MOVPSL

dst

dst ← PSL

MOVw Processor Status Longword


SYSTEM AND MISCELLANEOUS INSTRUCTIONS

(see Chapter 14 and VAX Architecture Handbook)

ADAWI

add,sum

ADd Aligned Word Interlocked

BBCCI

off,adr,disp

Branch - Bit Clear and Clear Interlocked

BBSSI

off,adr,disp

Branch - Bit Set and Set Interlocked

BPT

 

Break Point faulT (for debugging)

BUGx

 

BUGcheck (x = Word or Long)

CHMx

param

CHange Mode (x = Kernel, Executive, Supervisor, or User)

ESCx

 

ESCape (x = D, E, or F)

HALT

 

HALT processor

LDPCTX

 

LoaD Process ConTeXt

MFPR

src,reg

Move From special Processor Register

MTPR

reg,dst

Move To special Processor Register

NOP

 

No OPeration

PROBER

mode,len,base

PROBE Read accessibility in mode

PROBEW

mode,len,base

PROBE Write accessibility in mode

REI

 

Return from Exception or Interrupt

SVPCTX

 

SaVe Process ConTeXt

XFC

 

Extended Function Call


POWERS OF 2 and 16

16n

n

2n

1

0

1

16

1

2

256

2

4

4,096

3

8

65,536

4

16

1,048,576

5

32

16,777,216

6

64

268,435,456

7

128

4,294,967,296

8

256

68,719,476,736

9

512

1,099,511,627,776

10

1,024

17,592,186,044,416

11

2,048

281,474,976,710,656

12

4,096

4,503,599,627,370,496

13

8,192

72,057,594,037,927,936

14

16,384

1,152,921,504,606,846,976

15

32,768

18,446,744,073,709,551,616

16

65,536


ADDRESSING MODES SELECTED BY THE ASSEMBLER

Name

Assembler

Description

immediate

#constant

literal or immediate

displacement

DISP(Rx)

byte, word, or long displacement

disp. deferred

@DISP(Rx)

byte, word, or lung displacement deferred

relative

address

byte, word, or long relative addressing

rel. deferred

@address

byte, word, or long relative deferred


7-BIT ASCII CODE

Hex
Code

ASCII
Char

Hex
Code

ASCII
Char

Hex
Code

ASCII
Char

Hex
Code

ASCII
Char

00

NUL

20

SP

40

@

60

`

01

SOH

21

!

41

А

61

а

02

STX

22

"

42

В

62

b

03

ЕТХ

23

#

43

С

63

с

04

EOT

24

$

44

D

64

d

05

ENQ

25

%

45

Е

65

е

06

АСК

26

&

46

F

66

f

07

BEL

27

'

47

G

67

g

08

BS

28

(

48

Н

68

h

09

HT

29

)

49

I

69

i

LF

2A

*

J

j

VT

2B

+

К

k

FF

2C

,

L

l

0D

CR

2D

-

4D

М

6D

m

SO

2E

.

N

n

0F

SI

2F

/

4F

О

6F

o

10

DLE

30

0

50

Р

70

p

11

DC1

31

1

51

Q

71

q

12

DC2

32

2

52

R

72

r

13

DC3

33

3

53

S

73

s

14

DC4

34

4

54

Т

74

t

15

NAK

35

5

55

U

75

u

16

SYN

36

6

56

V

76

v

17

ETB

37

7

57

W

77

w

18

CAN

38

8

58

X

78

x

19

EM

39

9

59

Y

79

y

SUB

3A

:

Z

z

ESC

3B

;

[

{

1C

FS

3C

\

|

1D

GS

3D

=

5D

]

7D

}

RS

3E

^

~

1F

US

3F

?

5F

_

7F

DEL


GENERAL ADDRESSING MODES

(Rx is a general register R0 to R15)

(In descriptions, (Rx) means the contents of register Rx)

Hex

Dec

Name

Assembler

Description

0-3

0-3

literal

S^#literal

literal is operand

4

4

indexed

mode[Rx]

adr(mode)+n*(Rx) is adr

5

5

register

Rx

(Rx) is operand

6

6

reg deferred

(Rx)

(Rx) is address of oper

7

7

autodecrement

-(Rx)

dec Rx, Rx contains adr

8

8

autoincrement

(Rx)+

Rx contains adr, inc Rx

9

9

autoinc. def.

@(Rx)+

Rx contains adr of adr

A

10

byte disp.

B^DISP(Rx)

DISP+(Rx) is adr

B

11

byte disp. def.

@B^DISP(Rx)

DISP+(Rx) is adr of adr

C

12

word disp.

W^DISP(Rx)

DISP+(Rx) is adr

D

13

word disp. def.

@W^DISP(Rx)

DISP+(Rx) is adr of adr

E

14

long disp.

L^DISP(Rx)

DISP+(Rx) is adr

F

15

long disp. def.

@L^DISP(Rx)

DISP+(Rx) is adr of adr


PROGRAM COUNTER ADDRESSING MODES (Rx is PC or Register 15)

Hex

Dec

Name

Assembler

Description

8

8

immediate

I^#constant

constant is operand

9

9

absolute

@#address

address is adr of oper

A

10

byte relative

B^address

address is adr of oper

B

11

byte rel. def.

@B^address

address is adr of adr

C

12

word relative

W^address

address is adr of oper

D

13

word rel. def.

@W^address

address is adr of adr

E

14

long relative

L^address

address is adr of oper

F

15

long rel. def.

@L^address

address is adr of adr